Casio to Establish EWLP Consortium
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Casio
to Establish EWLP Consortium |
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January 12, 2006—Casio Computer Co., Ltd., announced plans today
to form the EWLP Consortium in April this year. The Consortium will
work toward the establishment and standardization of EWLP technology.
Embedded wafer level package (EWLP) technology is a sophisticated
packaging technique that enables a reduction in the overall size,
thickness, and weight of system boards by embedding wafer level packages
(WLP) into them. Casio kicked off EWLP technical development jointly
with Japanese board manufacturer CMK Corporation in 2002.
EWLP technology is expected to continue to develop in the future,
and is a hot topic in the industry. The EWLP Consortium is being established
as a platform for discussing and resolving common EWLP issues, in
order to establish EWLP as a standard industry technology that can
be widely used. |
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| Purposes
of establishing the EWLP Consortium, and its role |
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| 1. |
Cross-industry
technical exchange, and establishment of design
technology, modeling and simulation technology,
test technology, and reliability assessment technology
for EWLP, all of which are common issues. |
| 2. |
Proposal
of infrastructure improvements, including materials,
manufacturing equipment, and assessment facilities,
for establishing EWLP technology. |
| 3. |
Standardization
of WLP specifications in order to facilitate EWLP
manufacture and optimization of such things as distribution,
test methods, and shipment forms. |
| 4. |
Formulation
of an EWLP technology roadmap for promoting component
embedding technology. |
| 5. |
Development
and evaluation of a reference model with an actual
product in mind. |
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| Overview
of EWLP Consortium |
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| Name: |
EWLP
Consortium |
| Address: |
3-2-2
Fujihashi, Ome-shi, Tokyo, Japan (at Casio Computer
Co., Ltd.) |
| Chairman: |
Eiichi
Takeuchi (Corporate Officer, Casio Computer Co.,
Ltd.) |
| Established: |
Scheduled
for April 1, 2006 |
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The scheduled establishment of the Consortium is receiving support
from board manufacturers, including the above-mentioned CMK Corporation,
as well as many other manufacturers in various fields, including semiconductors,
modules, sets, and facilities.
EWLP technology will enable even further high-density packaging for
boards. It is expected to have broad practical applications, including
mobile devices such as cellular phones, SiP and various types of modules
which are showing strong demand for high-density/high functionality,
and in-vehicle devices that demand high reliability.
By establishing the EWLP Consortium, Casio will promote EWLP to the
rest of the world as a technology originating in Japan.
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At
the Casio Micronics booth, which will be set up at the IC Packaging
Technology Expo (January 18 to 20, 2005) at Tokyo Big Sight,
the company plans to exhibit an EWLP sample (a One Seg.Digital
TV tuner) developed jointly with CMK Corporation. |
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EWLP
module (development prototype of a One Seg.Digital TV
tuner module)
An OFDM WLP is embedded in the board, with a TUNER WLP
and other components mounted on the board.
(size: 8.2mm×9.2mm) |
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OFDM
WLP
(size: 6.5mm×6.5mm) |
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TUNER
WLP
(size: 3.1mm×3.1mm) |
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| Wafer
level package (WLP) |
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An
LSI package that enables copper rewiring, the formation of electrode
terminals, and resin encapsulation, all at the wafer level.
Enables a reduction in the mounting area of various types of
semiconductors, thanks to its reduction of LSI package size
to that of a semiconductor chip. Also enables the simultaneous
formation of passive components, such as inductors and resistors,
on the chip, and achieves the size/weight reduction and increased
functionality demanded by portable information devices and other
such devices at a low cost. |
| Embedded
wafer level package (EWLP) |
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A
technology that embeds WLPs on a system board. Aims to further
increase the performance and reduce the size, thickness, and
weight of electronic devices. Seeks to optimize semiconductors,
packages, and mounting boards, among other things. A wide range
of applications is expected thanks to the simplicity, low cost,
and high reliability of its solution technology compared to
the current complex technology. Not only enables the embedding
of multiple WLPs on a board, but also allows the mounting of
passive components on the board’s surface as well as the
layering of multiple boards. |
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System in package (SiP) |
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A
technique for mounting multiple LSI chips and passive components
in a single package such that they function as a system. |
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